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WM2130 10-bit 30msps analogue-to-digital converter production data, april 2001, rev 1.2 wolfson microelectronics ltd lutton court, bernard terrace, edinburgh, eh8 9nx, uk tel: +44 (0) 131 667 9386 fax: +44 (0) 131 667 5176 email: sales@wolfson.co.uk www.wolfsonmicro.com production data datasheets contain final specifications current on publication date. supply of products conforms to wolfson microelectronics? terms and conditions. ? 2001 wolfson microelectronics ltd. description the WM2130 is a high speed 10-bit analogue-to-digital converter and operates with independent analogue and digital supplies of 3v to 5.5v. this device includes a high bandwidth sample and hold and internal voltage references. conversion is controlled by a single clock input. the differential-input sample and hold input gives excellent common-mode noise immunity and low distortion. the device can also be driven in a single ended fashion. the device provides internal reference voltages for setting the adc full-scale range without the requirement for external circuitry. the WM2130 can also accept external reference levels for applications where higher precision references are required. the WM2130 has also been designed to offer a speed upgrade to users of the ad876 and a replacement for the ad9200 and ad9202 devices. the WM2130 operates as an ad876 in those design slots but at speeds of up to 50% faster. features ? 10-bit resolution adc ? 30msps conversion rate ? wide input bandwidth (150 mhz full-power bandwidth) sample and hold input amplifier ? independent analogue and digital supplies ? adjustable internal voltage references ? out of range indicator ? low power: 87mw typical at 3v supplies ? powerdown mode to 3mw typical ? 28-pin tssop package applications ? set top box (stb) ? if and baseband digitisation ? medical imaging ? high speed data acquisition block diagram WM2130 ain precision reference circuits + sha - refts d[9:0] refbf reftf ovr refbs oeb mode refsense power-down control stby agnd avdd dgnd dvdd m876b timing control clk output buffers adc
WM2130 production data wolfson microelectronics ltd pd rev 1.2 april 2001 2 pin configuration ordering information device temp. range package WM2130cdt/v 0 to +70 o c 28-pin tssop WM2130idt/v -40 to +85 o c 28-pin tssop 16 15 14 20 19 18 17 5 6 7 1 2 3 4 13 12 11 8 9 10 dio0 ovr oeb agnd dvdd refts refbs refbf reftf mode vref ain avdd dio8 refsense dio2 dio3 dio1 dio7 agnd dio6 dio5 m876b dio4 21 22 23 24 25 26 27 28 dio9 dgnd stby clk pin description pin name type description 1 agnd ground analogue ground 2 dvdd supply positive digital supply 3 do0 digital output digital output bit 0 (lsb) 4 do1 digital output digital output bit 1 5 do2 digital output digital output bit 2 6 do3 digital output digital output bit 3 7 do4 digital output digital output bit 4 8 do5 digital output digital output bit 5 9 do6 digital output digital output bit 6 10 do7 digital output digital output bit 7 11 do8 digital output digital output bit 8 12 do9 digital output digital output bit 9 (msb) 13 ovr digital output over-range output (tri-statable) 14 dgnd ground digital ground 15 clk digital input clock input 16 stby digital input powerdown control 17 oeb digital input output enable bar ? low to enable do[9:0] and ovr 18 refsense analogue input/output vref mode control 19 agnd ground negative analogue supply 20 m876b digital input ad876 mode select 21 refts analogue input top reference sense 22 reftf analogue input/output top reference force 23 mode digital input input mode select 24 refbf analogue input/output bottom reference force 25 refbs analogue input bottom reference sense 26 vref analogue input/output internal reference output 27 ain analogue input analog input 28 avdd supply positive analogue supply
production data WM2130 wolfson microelectronics ltd pd rev 1.2 april 2001 3 absolute maximum ratings absolute maximum ratings are stress ratings only. permanent damage to the device may be caused by continuously operating at or beyond these limits. device functional operating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of this device. as per specifications ipc/jedec j-std-020a and jedec a113-b, this product requires specific storage conditions prior to surface mount assembly. it has been classified as having a moisture sensitivity level of 2 and as such will be supplied in vacuum-sealed moisture barrier bags. condition min max digital supply voltage, dvdd to dgnd -0.3v +6.5v analogue supply voltage, avdd to agnd -0.3v +6.5v supply voltage difference, avdd to dvdd -6.5v +6.5v ground difference, agnd to dgnd -0.3v +0.3v digital inputs voltage range (do[9:0], stby, oeb, m876b) dgnd - 0.3v dvdd + 0.3v voltage range analogue inputs (refts, refbs, reftf, refbf, ain, vref, refsense, clk, mode) agnd - 0.3v avdd + 0.3v storage temperature -65 c +150 c soldering lead temperature, 1.6mm (1/16 inch) from package body for 10 seconds +300 c recommended operating conditions parameter symbol test conditions min nom max unit digital supply range dvdd 3.0 3.3 5.5 v analogue supply range avdd 3.0 3.3 5.5 v clock frequency f clk 530mhz clock duty cycle 45 50 55 % WM2130c 0 c operating free air minimum temperature t min WM2130i -40 c WM2130c 70 c operating free air maximum temperature t max WM2130i 85 c
WM2130 production data wolfson microelectronics ltd pd rev 1.2 april 2001 4 electrical characteristics test conditions: avdd = dvdd = 3.0v, f clk = 30mhz, 50% duty cycle, mode = avdd, refts = 2.5v, refbs = 0.5v, t a = t min to t max , unless otherwise stated. parameter symbol test conditions min typ max unit dc accuracy integral nonlinearity inl 1.0 2.0 lsb differential nonlinearity dnl 0.3 1.0 lsb offset error 0.4 2.0 % of fs gain error 1.4 3.5 % of fs missing codes no missing codes guaranteed analogue input signal to ain pin mode = agnd refbs refts v mode = avdd / 2, v cmcs fixed v cmcs ? vref/2 v cmcs + vref/2 v input signal range mode = avdd refbs refts v ain voltage limits agnd avdd v switched input capacitance 1.2 pf analogue input bandwidth 150 mhz dc leakage current full-scale input 60 a aperture delay t a 4ns aperture jitter 2ps rms conversion characteristics conversion frequency f clk 530mhz pipeline delay 3 clk cycles aperture delay t a 4ns aperture jitter 2ps rms dynamic performance f in = 3.5mhz 8.4 9 f in =3.5mhz, avdd 5v 9 f in = 15mhz 7.8 effective number of bits enob f in =15mhz, avdd 5v 7.7 db f in = 3.5mhz 56 60.6 f in =3.5mhz, avdd 5v 64.6 f in = 15mhz 48.5 spurious free dynamic range sfdr f in =15mhz, avdd 5v 53 db f in = 3.5mhz -60 -56 f in =3.5mhz, avdd 5v -66.9 f in = 15mhz -47.5 total harmonic distortion thd f in =15mhz, avdd 5v -53.1 db f in = 3.5mhz 53 57 f in =3.5mhz, avdd 5v 56 f in = 15mhz 53.1 signal to noise ratio snr f in =15mhz, avdd 5v 49.4 db f in = 3.5mhz 52.5 56 f in =3.5mhz, avdd 5v 56 f in = 15mhz 48.6 signal to noise and distortion ratio sinad f in =15mhz, avdd 5v 48.1 db
production data WM2130 wolfson microelectronics ltd pd rev 1.2 april 2001 5 test conditions: avdd = dvdd = 3.0v, f clk = 30mhz, 50% duty cycle, mode = avdd, refts = 2.5v, refbs = 0.5v, t a = t min to t max , unless otherwise stated. parameter symbol test conditions min typ max unit analogue reference inputs / outputs in top/bottom mode (mode=avdd) bottom reference voltage applied to refbs 0 avdd ? 1v top reference voltage applied to refts 1 avdd v differential reference input (refts ? refbs) v tb 12v switched input capacitance on refbs 0.6 pf switched input capacitance on refts 0.6 pf refbf output voltage (avdd - v tb )/2 v reftf output voltage (avdd + v tb )/2 v analogue reference inputs / outputs in centre-span mode (mode=avdd/2) reference voltage derived or applied to vref 12v refbf output voltage (avdd - vref)/2 v reftf output voltage (avdd + vref)/2 v analogue reference inputs / outputs in full external reference mode (mode=agnd) (note 1) differential reference voltage applied (reftf ? refbf) 12v avdd = 3.0v 1.3 1.5 1.7 v reference input common mode (reftf + refbf) / 2 avdd = 5.0v 2.0 2.5 3.0 v reference input resistance 680 ? vref input / output specifications internal 1v reference to vref refsense = vref 0.95 1.0 1.05 v internal 2v reference to vref refsense = agnd 1.9 2.0 2.1 v external reference applied to vref pin in centre-span mode refsense = avdd, mode = avdd / 2 12v input impedance in centre-span mode refsense = avdd, mode = avdd / 2 18 k ? power supplies avdd = dvdd = 3v, mode = agnd 29 40 operating supply current i avdd + i dvdd avdd = dvdd = 5v 50 ma standby power p stby avdd = dvdd = 3v, mode = agnd 35mw digital logic levels (cmos levels) input low level v il (note 2) 0.2 x vdd v input high level v ih (note 2) 0.8 x vdd v notes 1. in full external reference mode the reftf and refts pins should be shorted together, and the refbf and refbs pins should be shorted together. please refer to device operation examples in the device description section of the datasheet. 2. digital input and output levels refer to the supply used for the input/output buffer on the relevant pin. mode refers to the avdd supply, all other digital input/output refers to the dvdd supply.
WM2130 production data wolfson microelectronics ltd pd rev 1.2 april 2001 6 sample 1 sample 5 sample 4 sample 3 sample 2 t clk t cl t ch digital output t d pipeline delay sample 1 sample 2 note: all timing measurements are based on 50% of edge transition clk analogue input at ain figure 1 output timing test conditions: avdd = dvdd = 3.0v, f clk = 30mhz, 50% duty cycle, mode = avdd, refts = 2.5v, refbs = 0.5v, t a = t min to t max , unless otherwise stated. parameter symbol test conditions min typ max unit clock clock period t clk 33 ns clock high time t ch 15 16.5 ns clock low time t cl 15 16.5 ns timing pipeline delay 3 clk cycles clock to data valid t d 25 ns output disable to hi-z output t dz 020ns output enable to data valid t den 020ns
production data WM2130 wolfson microelectronics ltd pd rev 1.2 april 2001 7 typical system performance avdd = dvdd = 3v, f s = 30 msps -1 -0.75 -0.5 -0.25 0 0.25 0.5 0.75 1 0 128 256 384 512 640 768 896 1024 digital code differential non-linearity (lsbs) figure 2 differential non-linearity avdd = dvdd = 3v, f s = 30msps -3 -2 -1 0 1 2 3 0 128 256 384 512 640 768 896 1024 digital code integral non-linearity (lsbs) figure 3 integral non-linearity -140 -120 -100 -80 -60 -40 -20 0 0 3 6 9 12 15 frequency (mhz) fft (db) avdd = dvdd = 3v, f in = 3.58mhz, -1db fs figure 4 fast fourier transform (fft)
WM2130 production data wolfson microelectronics ltd pd rev 1.2 april 2001 8 device description introduction the WM2130 is a high speed analogue-to-digital converter (adc) with on-chip sample and hold and reference generation, designed for applications such as composite video digitisation, digital copiers and and high speed data acquisition. the chip architecture consists of: ? high bandwidth sample and hold input, which can operate in differential or single- ended mode ? 10-bit, 30msps pipeline analogue-to-digital converter (adc) core ? on-chip reference generator and reference buffer (external references can also be used for applications where common or high precision references are required) ? 10-bit parallel interface to read adc conversion data. an out-of-range output pin indicates when the input signal is outside the converter ? s range (this is disabled in ad876 compatible mode). analogue signal path the WM2130 analogue signal path consists of a dc clamp with a 10-bit clamp level dac (discussed under ? dc clamp ? , below), a high-bandwidth sample and hold unit and a fast 10-bit pipelined analogue to digital converter (adc core). sample and hold refts refbs ain -1/2 +1 -1/2 reftf refbf adc core vq+ vq- figure 5 analogue input signal flow figure 5 shows the signal flow through the sample and hold unit to the adc core, where the process of analogue to digital conversion is performed against the adc reference voltages, reftf and refbf (their generation from internal or external reference sources is described later). sample and hold the analogue input voltage v in is applied to the ain pin, either dc coupled or ac coupled. the differential sample and hold processes v in with respect to the voltages applied to the refts and refbs pins, and produces a differential output v q = v q+ - v q- given by: m in q v v v ? = where 2 refbs refts v m + = for single-ended input signals, v m is a constant voltage; usually the ain mid-scale input voltage. however, in differential mode (see ? adc reference modes ? , below), refts and refbs can be connected together to operate with ain as a complementary pair of differential inputs.
production data WM2130 wolfson microelectronics ltd pd rev 1.2 april 2001 9 analogue-to-digital converter regardless of the reference configuration, v q is digitised against adc reference voltages reftf and refbf, full scale values of v q being given by: 2 refbf reftf v qfs ? = + and ? ? ? ? ? ? ? ? = ? 2 refbf reftf v qfs attempts to convert v q voltages outside the range of v qfs- to v qfs+ are signalled to the application by driving the ovr output pin high. if v q is less than v qfs- , the adc output code is 0. if v q is greater than v qfs+ , the output code is 1023. signal chain summary combining the above equations and referring back to the input, the positive and negative full-scale voltages at the ain pin are: 2 refbf reftf v v m infs ? + = + and 2 refbf reftf v v m infs ? ? = ? therefore the input signal span is given by: refbf reftf v v infs infs ? = ? ? + in order to match the adc input range to the input signal amplitude, reftf and refbf should be set such that: ) ( ? + ? = ? infs infs v v refbf reftf adc reference modes the WM2130 supports three basic modes of reference generation, selected by the voltage applied to the mode pin. these are summarised and explained in table 1. in differential, centre span and top/bottom modes, the internally generated adc references are intened solely for WM2130 internal use and reftf and refbf must not be used as voltage references for any other device in the application. mode pin mode function comments agnd full external refts reftf = refbs refbf = on-chip reference generator and reference buffer are not used. avdd/2 differential 2 ref v avdd reftf + = 2 ref v avdd reftf ? = v ref can be internally or externally generated. refts and refbs are joined together and connected either to the negative end of the input signal (true differential mode) or to the ain mid-scale voltage (centre-span mode). avdd top/bottom () 2 refbs refts avdd reftf ? + = () 2 refbs refts avdd refbf ? ? = on-chip reference generator is not used. reference buffer centers external reference voltages around avdd/2. table 1 WM2130 reference generation modes
WM2130 production data wolfson microelectronics ltd pd rev 1.2 april 2001 10 full external reference mode (mode = agnd) when mode is connected to agnd, the WM2130 operates in full external reference mode. the internal reference buffer is powered down and bypassed, so that the adc core takes the user- supplied reference voltages at pins refts and refbs (refts and refbs are internally connected to reftf and refbf). the mean of reftf and refbf must be equal to avdd/2. only single-ended input is possible in this mode. refts refbs ain reftf refbf adc core sample and hold -1/2 +1 -1/2 internal reference buffer figure 6 adc reference generation in full external mode the full external mode of operation is useful when the application requires more accurate or lower drift reference voltages than the WM2130 can provide, or when devices need to share common reference voltages for best adc matching. it also offers the possibility of using refts and refbs as sense lines to drive the reftf and refbf lines ( kelvin mode ) to eliminate any voltage drops from remote references within the system (see figure 7). in kelvin configurations, take care when choosing the external op-amps to ensure that they can drive large capacitive loads without oscillating. although the on-chip reference generator is not used by the WM2130 in full external mode, its output is available on the vref pin and can be used by other parts of the system. note that in addition to the internal connections from refts to reftf and refbs to refbf, external wire connections must also be made as shown in figure 8 to minimise resistance (except in kelvin mode). avdd/2 avdd ain mode refsense dc source = avdd/2 + [(+fs) - (-fs)] * gain/2 dc source = avdd/2 - [(+fs) - (-fs)] * gain/2 reftf refbf +fs -fs refts refbs 0.1f 10f 0.1f 0.1f figure 7 full external reference mode (reference generator disabled)
production data WM2130 wolfson microelectronics ltd pd rev 1.2 april 2001 11 avdd/2 avdd ain mode refsense reftf refbf +fs -fs refts refbs - + + - reft = avdd/2 + [(+fs) - (-fs)] * gain/2 refb = avdd/2 - [(+fs) - (-fs)] * gain/2 0.1f 10f 0.1f 0.1f 0.1f 0.1f figure 8 full external mode with kelvin connections (reference generator disabled) differential mode (mode = avdd/2) the WM2130 operates in differential mode when the voltage at the mode pin is avdd/2 (mid- supply). the adc reference voltages reftf and refbf are generated by the internal reference buffer from v ref . depending on the connection of the refsense pin, v ref may be supplied by the on-chip reference generator or driven by an external source, as discussed under ? on-chip reference voltage generation ? , below. reftf and refbf are centred around avdd/2 by the internal reference buffer and the voltage difference between them equals v ref . refts refbs ain reftf refbf adc core internal reference buffer = avdd + vref 2 = avdd - vref 2 vref agnd sample and hold -1/2 +1 -1/2 figure 9 adc reference generation in differential mode this mode is suitable for handling differentially presented inputs, which are applied to the ain and refts/refbs pins. a special case of differential mode is centre span mode , in which the user applies a single-ended signal to ain and applies the mid-scale input voltage (v m ) to the refts and refbs pins. avdd/2 ain refsense reftf refbf +fs -fs refts refbs 0.1f 10f 0.1f 0.1f vref mode figure 10 differential mode, 1v reference span
WM2130 production data wolfson microelectronics ltd pd rev 1.2 april 2001 12 avdd/2 ain refsense +fs -fs refts refbs vm vm dc source =vm reftf refbf 0.1f 0.1f 0.1f 10f + - mode figure 11 centre span mode, 2v reference span top/bottom mode (mode = avdd) top/bottom mode is enabled by connecting the mode pin to avdd. in this mode, the adc reference voltages reftf and refbf are generated by the internal reference buffer from the externally supplied voltages refts and refbs. only single-ended input is possible in top/bottom mode. refts refbs ain reftf = avdd + (refts - refbs) adc core internal reference buffer refbf = avdd - (refts - refbs) sample and hold -1/2 +1 -1/2 figure 12 adc reference generation in top/bottom mode the voltage difference between refts and refbs should equal the peak-to-peak input signal amplitude. a smaller voltage difference would give rise to out-of-range conditions, whereas a larger one would not fully utilise the adc resolution. the average of refts and refbs must be the ain mid-scale voltage, v m . typically, refsense is tied to avdd to disable the on-chip reference generator, but the user can also choose to use its output to drive either refts or refbs. avdd ain refsense reftf refbf +fs -fs refts refbs mode dc source = vm + [(fs+) - (fs-)]* gain/2 dc source = vm - [(fs+) - (fs-)]* gain/2 0.1f 10f 0.1f 0.1f figure 13 top/bottom mode (reference generator disabled)
production data WM2130 wolfson microelectronics ltd pd rev 1.2 april 2001 13 on-chip reference voltage generator the on-chip reference generator (org) can provide a reference voltage on the vref pin that is independent of temperature and supply voltage. external connections to the refsense pin control the org ? s output to vref, as shown in figure 14. refsense connection org output to vref vref pin 1 volt agnd 2 volts external divider junction (1 + r a /r b ) volts ? see figure 14 avdd none (vref becomes input pin) table 2 controlling the on-chip reference generator connecting refsense to avdd powers the org down, saving power when the org function is not required. in differential mode (mode = avdd/2), the voltage on vref determines the adc reference voltages as follows: 2 ref v avdd reftf + = 2 ref v avdd refbf ? = ref v refbf reftf = ? when the org is enabled, the vref pin should be decoupled to the circuit board ? s analogue ground plane close to the WM2130 agnd pin via a 1 f tantalum capacitor and a 0.1 f ceramic capacitor. the org can source currents up to 1ma into external grounded loads when it is not used by the WM2130. typical buffer load regulation is about 0.5 ? . internal reference buffer 1f tantalum 0.1f v ref = 1 + (r a /r b ) refsense agnd vbg ? ? + + r b r a mode = avdd/2 figure 14 org operating with external divider (for intermediate reference voltages)
WM2130 production data wolfson microelectronics ltd pd rev 1.2 april 2001 14 power management in power-sensitive applications (such as battery-powered systems) where the WM2130 adc is not required to convert continuously, power can be saved between conversion intervals by placing the WM2130 into power down mode. this is achieved by pulling the standby mode pin (stby, pin 16) high. in power down mode, the device typically consumes less than 3mw of power. power down mode is exited by resetting control register bit 3 to 0. on power up from long periods of power down, the WM2130 typically requires 5ms of wake up time before valid conversion results are available. when refsense is tied to avdd, the reference generator is disabled and supply current reduced by approximately 1.2ma. digital output format while the oeb pin is held low, adc conversion results are output at the data output pins do0 (lsb) to do9 (msb). the output data format is unsigned binary (output codes 0 to 1023). ad876 compatibility mode pulling m876b (pin 20) low puts the WM2130 into ad876 compatibility mode. in this mode the device latency increases to 3.5 clock cycles and the ovr pin is tri-stated to avoid conflict with the drgnd connection present at pin 13 in ad876 slots. for best dynamic performance, use a 3 cycle latency operating mode if possible.
production data WM2130 wolfson microelectronics ltd pd rev 1.2 april 2001 15 applications information driving the clock input obtaining good performance from the WM2130 requires care when driving the clock input. different sections of the sample-and-hold and adc operate while the clock is low or high. the user should ensure that the clock duty cycle remains near 50% to ensure that all internal circuits have as much time as possible in which to operate. the clk pin should also be driven from a low jitter source for best dynamic performance. to maintain low jitter at the clk input, any clock buffers external to the WM2130 should have fast rising edges. use a fast logic family such as ac or act to drive the clk pin, and consider powering any clock buffers separately from any other logic on the pcb to prevent digital supply noise appearing on the buffered clock edges as jitter. as the clk input threshold is nominally around avdd/2, any clock buffers need to have an appropriate supply voltage to drive above and below this level. driving the sample and hold inputs driving the ain pin figure 15 shows an equivalent circuit for the WM2130 ain pin. the load presented to the system at the ain pin comprises the switched input sampling capacitor, c sample , and various stray capacitances, c p1 and c p2 . v last ain avdd agnd clk clk c p1 c sample 1.2pf + - c p2 = 1.2pf 8pf figure 15 equivalent circuit for analogue input pin ain the input current pulses required to charge c sample can be time averaged and the switched capacitor circuit modelled as an equivalent resistor clk s in f c r = 1 2 where c s is the sum of c sample and c p2 (see figure 16). this model can be used to estimate the input loading versus source resistance for high impedance sources. v m = (refts + refbs) /2 ain avdd agnd + - r in2 = 1 / c s f clk c p1 = 8pf i in figure 16 equivalent circuit for the ain switched capacitor input
WM2130 production data wolfson microelectronics ltd pd rev 1.2 april 2001 16 ain input damping the charging current pulses into ain can make the signal source jump or ring, especially if the source is slightly inductive at high frequencies. inserting a small series resistor of 20 ? or less in the input path can damp source ringing (see figure 17). the resistor can be made larger than 20 ? if reduced input bandwidth or distortion performance is acceptable. ain v s < 20r figure 17 damping source ringing using a small resistor driving the sample & hold reference inputs the sample and hold reference inputs (connected to pins refts and refbs) present switched- capacitor loads similar to the ain pin, but with smaller capacitors (see figure 18 below). note that in top/bottom mode, the internal reference buffer is also driven from refts and refbs and the total load on these pins is therefore the parallel combination of the sample and hold circuit and the reference buffer. refts or refbs avdd agnd mode = avdd v last c p1 internal reference buffer clk clk c sample 0.6pf + - c p2 = 0.6pf 7pf figure 18 equivalent circuit of refts and refbs sample & hold inputs
production data WM2130 wolfson microelectronics ltd pd rev 1.2 april 2001 17 driving the internal reference buffer driving the vref pin (differential mode) figure 19 shows the equivalent load on the vref pin when driving the internal reference buffer via this pin (mode = avdd/2 and refsense = avdd). vref refsense=avdd, mode = avdd/2 + - (avdd+vref) / 4 r in avdd agnd 14k figure 19 equivalent circuit of vref the input current i ref is given by in ref ref r avdd v i ? = 4 3 tolerance on this current is 30 % or greater. the user should ensure that vref is driven from a low noise, low drift source, well-decoupled to analogue ground and capable of driving i ref . driving the internal reference buffer (top/bottom mode) figure 20 shows the loading on the refts and refbs pins in top/bottom mode due to the internal reference buffer. note that the sample and hold circuit must also be driven via these pins, which adds additional load (see driving the sample & hold reference inputs, above). mode = avdd + - avdd + (refts + refbs) / 4 r in agnd 14k avdd refts or refbs figure 20 equivalent circuit of inputs to internal reference buffer the input currents are given by: in ints r refbs avdd refts i ? ? = 4 3 and in inbs r refts avdd refbs i ? ? = 4 3 these currents must be provided by the sources on refts and refbs in addition to the requirements of driving the sample and hold.
WM2130 production data wolfson microelectronics ltd pd rev 1.2 april 2001 18 driving reftf and refbf (full external reference mode) 680r avdd agnd avdd agnd reftf refbf to refbs (for kelvin connection) to refts (for kelvin connection) figure 21 equivalent circuit of reftf and refbf inputs reference decoupling vref pin when the on-chip reference generator is enabled, the vref pin should be decoupled to the circuit board ? s analogue ground plane close to the WM2130 agnd pin via a 1 f tantalum capacitor and a 0.1 f ceramic capacitor. reftf and refbf pins in any mode of operation, the reftf and refbf pins should be decoupled as shown in figure 22 below. use short board traces between the WM2130 and the capacitors to minimise parasitic inductance. wm2331 reftf refbf 0.1f 0.1f 0.1f 10f figure 22 recommended decoupling for the adc reference pins reftf and refbf supply decoupling the analogue (avdd, agnd) and digital (dvdd, dgnd) power supplies to the WM2130 should be separately decoupled for best performance. each supply needs at least a 10 f electrolytic or tantalum capacitor (as a charge reservoir) and a 100nf ceramic type capacitor placed as close as possible to the respective pins (to suppress spikes and supply noise).
production data WM2130 wolfson microelectronics ltd pd rev 1.2 april 2001 19 digital output loading and circuit board layout the WM2130 outputs are capable of driving rail-to-rail with up to 20pf of load per pin at 30mhz clock and 3v digital supply. minimising the load on the outputs will improve WM2130 signal-to-noise performance by reducing the switching noise coupling from the WM2130 output buffers to the internal analogue circuits. the output load capacitance can be minimised by buffering the WM2130 digital outputs with a low input capacitance buffer placed as close to the output pins as physically possible, and by using the shortest possible tra cks betw een the WM2130 and this buffer. noise levels at the output buffers, which may affect the analogue circuits within WM2130, increase with the digital supply voltage. where possible, consider using the lowest dvdd that the application can tolerate. use good layout practices when designing the application pcb to ensure that any off-chip return currents from the WM2130 digital outputs (and any other digital circuits on the pcb) do not return via the supplies to any sensitive analogue circuits. the WM2130 should be soldered directly to the pcb for best performance. socketing the device will degrade performance by adding parasitic socket inductance and capacitance to all pins. user tips for obtaining best performance from the WM2130 ? choose differential input mode for best distortion performance. ? choose a 2v adc input span for best noise performance. ? choose a 1v adc input span for best distortion performance. ? drive the clock input clk from a low-jitter, fast logic stage, with a well-decoupled power supply and short pcb traces.
WM2130 production data wolfson microelectronics ltd pd rev 1.2 april 2001 20 package dimensions notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0.25mm. d. meets jedec.95 mo-153, variation = ae. refer to this specification for further details. dm022.a dt: 28 pin tssop (9.7 x 4.4 x 1.0 mm) symbols dimensions (mm) min nom max a ----- ----- 1.20 a 1 0.05 ----- 0.15 a 2 0.80 1.00 1.05 b 0.19 ----- 0.30 c 0.09 ----- 0.20 d 9.60 9.70 9.80 e 0.65 bsc e 6.4 bsc e 1 4.30 4.40 4.50 l 0.45 0.60 0.75 0 o ----- 8 o ref: jedec.95, mo-153 c l gauge plane 0.25 15 28 e1 e e b 14 1 d seating plane a a2 a1 -c- 0.1 c

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